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yosys/backends/verilog
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whitequark 55c1f40277 verilog_backend: dump attributes on CaseRule, as comments. 
Attributes are not permitted in that position by Verilog grammar.
2019-07-08 12:48:50 +00:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc verilog_backend: dump attributes on CaseRule, as comments. 2019-07-08 12:48:50 +00:00