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yosys/techlibs/ecp5
whitequark 550310e264 Harmonize BRAM/LUTRAM descriptions across all of Yosys.
This commit:
  * renames all remaining instances of "DRAM" (which is ambiguous)
    to "LUTRAM" (which is not), finishing the work started in
    the commit 698ab9be;
  * renames memory rule files to brams.txt/lutrams.txt;
  * adds/renames script labels map_bram/map_lutram;
  * extracts where necessary script labels map_ffram and map_gates;
  * adds where necessary options -nobram/-nolutram.

The end result is that BRAM/LUTRAM/FFRAM aspects of every target
are now consistent with each other.

Per architecture:
  * anlogic: rename drams.txt→lutrams.txt, add -nolutram, add
    :map_lutram, :map_ffram, :map_gates
  * ecp5: rename bram.txt→brams.txt, lutram.txt→lutrams.txt
  * efinix: rename bram.txt→brams.txt, add -nobram, add :map_ffram,
    :map_gates
  * gowin: rename bram.txt→brams.txt, dram.txt→lutrams.txt,
    rename -nodram→-nolutram (-nodram still recognized), rename
    :bram→:map_bram, :dram→:map_lutram, add :map_ffram, :map_gates
2020-01-01 12:30:00 +00:00
..
tests ecp5: Add simulation equivalence check for Diamond FF implementations 2019-08-30 13:27:36 +01:00
.gitignore ecp5: Add support for mapping 36-bit wide PDP BRAMs 2019-10-01 13:46:36 +01:00
abc9_5g.box Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
abc9_5g.lut Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
abc9_5g_nowide.lut Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
abc9_map.v Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
abc9_model.v Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
abc9_unmap.v Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
arith_map.v ecp5: Improve mapping of $alu when BI is used 2019-06-21 09:45:11 +01:00
brams.txt Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
brams_connect.py ecp5: Add support for mapping 36-bit wide PDP BRAMs 2019-10-01 13:46:36 +01:00
brams_init.py ecp5: First BRAM type maps successfully 2018-10-10 16:35:19 +01:00
brams_map.v ecp5: Add support for mapping 36-bit wide PDP BRAMs 2019-10-01 13:46:36 +01:00
cells_bb.v ecp5: Add ECLKBRIDGECS blackbox 2019-10-11 14:50:33 +01:00
cells_ff.vh Fix bitwidth mismatch; suppresses iverilog warning 2019-12-11 13:02:07 -08:00
cells_io.vh ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives. 2019-08-30 10:05:09 +00:00
cells_map.v ecp5: Add support for mapping PRLD FFs 2019-12-07 13:04:36 +00:00
cells_sim.v Nitpick cleanup for ecp5 2019-12-27 16:57:08 -08:00
dsp_map.v ecp5: Bring up to date with mul2dsp changes 2019-08-08 15:14:09 +01:00
ecp5_ffinit.cc ecp5: Demote conflicting FF init values to a warning 2019-03-04 11:26:20 +00:00
ecp5_gsr.cc ecp5_gsr: Fix typo 2019-08-31 09:58:46 +01:00
latches_map.v ecp5: Add latch inference 2018-10-19 15:16:40 +01:00
lutrams.txt Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
lutrams_map.v synth_ecp5: rename dram to lutram everywhere. 2019-07-16 20:45:12 +00:00
Makefile.inc Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00
synth_ecp5.cc Harmonize BRAM/LUTRAM descriptions across all of Yosys. 2020-01-01 12:30:00 +00:00