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Code Activity
yosys/tests/proc
History
Marcelina Kościelnicka a55bf6375b proc_arst: Add special-casing of clock signal in conditionals. 
The already-existing special case for conditionals on clock has been
remade as follows:

- now triggered for the last remaining edge trigger after all others
  have been converted to async reset, not just when there is only one
  sync rule in the first place
- does not require all contained assignments to be constant, as opposed
  to a reset conditional — merely const-folds the condition

In addition, the code has been refactored a bit; as a bonus, the
priority order of async resets found is now preserved in resulting sync
rule ordering (though this is not yet respected by proc_dff).

Fixes #2656.
2021-03-15 17:17:29 +01:00
..
.gitignore proc_clean: fix order of switch insertion. 2019-08-19 16:44:23 +00:00
bug2619.ys proc_dff: Fix emitted FF when a register is not assigned in async reset 2021-03-08 17:01:43 +01:00
bug2656.ys proc_arst: Add special-casing of clock signal in conditionals. 2021-03-15 17:17:29 +01:00
bug_1268.v proc_clean: fix order of switch insertion. 2019-08-19 16:44:23 +00:00
bug_1268.ys proc_clean: fix order of switch insertion. 2019-08-19 16:44:23 +00:00
run-test.sh proc_clean: fix order of switch insertion. 2019-08-19 16:44:23 +00:00