yosys/tests/liberty/dff.lib.verilogsim.ok

module dff (D, CLK, Q);
  reg "IQ", "IQN";
  input D;
  input CLK;
  output Q;
  assign Q = IQ; // "IQ"
  always @(posedge CLK) begin
      // "(D)"
      "IQ" <= (D);
      "IQN" <= ~((D));
  end
endmodule