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https://github.com/YosysHQ/yosys
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36 lines
741 B
Text
36 lines
741 B
Text
pattern muldiv
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state <SigSpec> t x y
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match mul
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select mul->type == $mul
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select GetSize(port(mul, \A)) + GetSize(port(mul, \B)) <= GetSize(port(mul, \Y))
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endmatch
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code t x y
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t = port(mul, \Y);
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x = port(mul, \A);
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y = port(mul, \B);
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branch;
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std::swap(x, y);
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endcode
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match div
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select div->type.in($div)
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index <SigSpec> port(div, \A) === t
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index <SigSpec> port(div, \B) === x
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endmatch
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code
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SigSpec div_y = port(div, \Y);
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SigSpec val_y = y;
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if (GetSize(div_y) != GetSize(val_y))
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val_y.extend_u0(GetSize(div_y), param(div, \A_SIGNED).as_bool());
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did_something = true;
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log("muldiv pattern in %s: mul=%s, div=%s\n", log_id(module), log_id(mul), log_id(div));
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module->connect(div_y, val_y);
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autoremove(div);
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reject;
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endcode
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