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11 lines
188 B
Verilog
11 lines
188 B
Verilog
module \$__ABC9_FF_ (input D, output Q);
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endmodule
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(* abc9_box *)
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module \$__ABC9_DELAY (input I, output O);
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parameter DELAY = 0;
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specify
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(I => O) = DELAY;
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endspecify
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endmodule
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