mirror of
https://github.com/YosysHQ/yosys
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159 lines
5.5 KiB
ReStructuredText
159 lines
5.5 KiB
ReStructuredText
Compiling with Verific library
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==============================
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YosysHQ creates build for TabbyCAD Suite that includes Verific with additional
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patches and our own extensions library. However, if you have licensed Verific
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library in source or binary form you can still compile Yosys and have at least
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partial support.
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Compile options
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---------------
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To enable Verific support ``ENABLE_VERIFIC`` has to be set to ``1`` and
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``VERIFIC_DIR`` needs to point to location where library is located.
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============== ========================== ===============================
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Parameter Default Description
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============== ========================== ===============================
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ENABLE_VERIFIC 0 Enable compilation with Verific
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VERIFIC_DIR /usr/local/src/verific_lib Library and headers location
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============== ========================== ===============================
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Since there are multiple Verific library builds and they can have different
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features, there are compile options to select them.
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================================= ======= ===================================
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Parameter Default Description
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================================= ======= ===================================
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ENABLE_VERIFIC_SYSTEMVERILOG 1 SystemVerilog support
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ENABLE_VERIFIC_VHDL 1 VHDL support
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ENABLE_VERIFIC_HIER_TREE 1 Hierarchy tree support
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ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 1 YosysHQ specific extensions support
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ENABLE_VERIFIC_EDIF 0 EDIF support
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ENABLE_VERIFIC_LIBERTY 0 Liberty file support
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================================= ======= ===================================
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Supported build
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---------------
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Default options values are created in such way to represent supported build.
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This one includes SystemVerilog and VHDL support with RTL elaboration, hierarchy
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tree and static elaboration for both languages.
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Fully supported build includes additional YosysHQ patch that can be bought for
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**only** this Verific library configuration.
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NOTE: TabbyCAD builds also have additional EDIF and Liberty file support enabled
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as well. YosysHQ extensions library is only part of TabbyCAD as a product.
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Partialy supported builds
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-------------------------
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Note that these builds can be used with Yosys but will miss some of important
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features.
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1. SystemVerilog + RTL elaboration
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================================= =======
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Parameter Default
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================================= =======
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ENABLE_VERIFIC_SYSTEMVERILOG 1
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ENABLE_VERIFIC_VHDL 0
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ENABLE_VERIFIC_HIER_TREE 0
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ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
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================================= =======
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2. VHDL + RTL elaboration
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================================= =======
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Parameter Default
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================================= =======
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ENABLE_VERIFIC_SYSTEMVERILOG 0
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ENABLE_VERIFIC_VHDL 1
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ENABLE_VERIFIC_HIER_TREE 0
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ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
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================================= =======
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3. SystemVerilog + VHDL + RTL elaboration
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================================= =======
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Parameter Default
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================================= =======
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ENABLE_VERIFIC_SYSTEMVERILOG 1
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ENABLE_VERIFIC_VHDL 1
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ENABLE_VERIFIC_HIER_TREE 0
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ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
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================================= =======
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3. SystemVerilog + RTL elaboration + Static elaboration + Hier tree
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================================= =======
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Parameter Default
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================================= =======
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ENABLE_VERIFIC_SYSTEMVERILOG 1
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ENABLE_VERIFIC_VHDL 0
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ENABLE_VERIFIC_HIER_TREE 1
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ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
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================================= =======
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3. VHDL + RTL elaboration + Static elaboration + Hier tree
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================================= =======
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Parameter Default
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================================= =======
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ENABLE_VERIFIC_SYSTEMVERILOG 0
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ENABLE_VERIFIC_VHDL 1
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ENABLE_VERIFIC_HIER_TREE 1
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ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
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================================= =======
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4. SystemVerilog + VHDL + RTL elaboration + Static elaboration + Hier
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tree
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================================= =======
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Parameter Default
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================================= =======
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ENABLE_VERIFIC_SYSTEMVERILOG 1
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ENABLE_VERIFIC_VHDL 1
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ENABLE_VERIFIC_HIER_TREE 1
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ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS 0
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================================= =======
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NOTE:
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In case your Verific build have EDIF and/or Liberty support, you can enable
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those options, these are not mentioned above for simplification and since they
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are disabled by default.
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NOTE: To be able to compile Yosys+Verific you need Verific library that have at
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least one of HDL languages support with RTL elaboration enabled. Please note
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that without YosysHQ specific extensions of Verific library, support is limited.
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Verific Features that should be enabled in your Verific library
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===============================================================
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Please be aware that next Verific configuration build parameter needs to be
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enabled in order to create fully supported build.
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::
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database/DBCompileFlags.h:
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DB_PRESERVE_INITIAL_VALUE
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Additional features included with Yosys Verific patch
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=====================================================
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New cells
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---------
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============== ===========
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Cell Description
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============== ===========
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$initstate
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$set_tag
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$get_tag
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$overwrite_tag
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$original_tag
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$future_ff
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============== ===========
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