3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-22 04:12:06 +00:00
yosys/techlibs/common
Krystine Sherwin 27b8b4e81e
Docs: Fix missing groups
$lut and $sop were missed in the rebase, and $buf is new to main since the last rebase.
2024-10-15 11:08:30 +13:00
..
choices techmap: Note down iteration in Kogge-Stone 2024-04-08 16:45:40 +02:00
.gitignore
abc9_map.v
abc9_model.v
abc9_unmap.v
adff2dff.v
cellhelp.py cellhelp.py: Cells can have tags 2024-10-15 07:35:41 +13:00
cells.lib
cmp2lcu.v
cmp2lut.v
cmp2softlogic.v techlibs: Add cmp2softlogic.v to common 2023-11-13 10:42:12 +01:00
dff2ff.v
gate2lut.v
gen_fine_ffs.py simcells: Apply group tags 2024-10-15 07:35:40 +13:00
Makefile.inc techmap: Split out Kogge-Stone into a separate file 2024-03-27 11:07:24 +01:00
mul2dsp.v
pmux2mux.v
prep.cc Run future as part of prep 2023-09-13 11:32:36 +02:00
simcells.v Docs: Assert cell has group 2024-10-15 07:35:40 +13:00
simlib.v Docs: Fix missing groups 2024-10-15 11:08:30 +13:00
smtmap.v Add smtmap.v describing the smt2 backend's behavior for undef bits 2022-10-20 15:48:18 +02:00
synth.cc synth: Fix out-of-sync help message 2024-03-06 14:55:43 +01:00
techmap.v quicklogic: Avoid carry chains in division mapping 2024-09-19 12:18:47 +02:00