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yosys/techlibs/xilinx/cells.box
2019-04-09 14:32:10 -07:00

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# Max delays from https://pastebin.com/v2hrcksd
# from https://github.com/SymbiFlow/prjxray/pull/706#issuecomment-479380321
# F7BMUX slower than F7AMUX
# Inputs: 0 1 S0
# Outputs: OUT
F7BMUX 1 0 3 1
217 223 296
# Inputs: 0 1 S0
# Outputs: OUT
MUXF8 2 0 3 1
104 94 273