Ruben Undheim c50afc4246 Documentation improvements etc. ... - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)		2018-10-13 20:34:44 +02:00
..
hierarchy.cc	Documentation improvements etc.	2018-10-13 20:34:44 +02:00
Makefile.inc	Rename "singleton" pass to "uniquify"	2017-08-20 12:31:50 +02:00
submod.cc	Consistent use of 'override' for virtual methods in derived classes.	2018-07-20 23:51:06 -07:00
uniquify.cc	Consistent use of 'override' for virtual methods in derived classes.	2018-07-20 23:51:06 -07:00