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yosys/frontends/verilog
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Udi Finkelstein 536ae16c3a Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
2018-10-25 02:37:56 +03:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
const2ast.cc Convert more log_error() to log_file_error() where possible. 2018-07-20 09:37:44 -07:00
Makefile.inc Add "make coverage" 2018-08-27 14:22:21 +02:00
preproc.cc Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
verilog_frontend.cc Add "read_verilog -noassert -noassume -assert-assumes" 2018-09-24 20:51:16 +02:00
verilog_frontend.h Add "read_verilog -noassert -noassume -assert-assumes" 2018-09-24 20:51:16 +02:00
verilog_lexer.l Merge pull request #659 from rubund/sv_interfaces 2018-10-18 10:58:47 +02:00
verilog_parser.y Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique, 2018-10-25 02:37:56 +03:00