mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
347dd01c2f
Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly. |
||
|---|---|---|
| .. | ||
| achronix | ||
| anlogic | ||
| common | ||
| coolrunner2 | ||
| easic | ||
| ecp5 | ||
| efinix | ||
| gowin | ||
| greenpak4 | ||
| ice40 | ||
| intel | ||
| intel_alm | ||
| sf2 | ||
| xilinx | ||
| .gitignore | ||