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yosys/frontends/verilog
clairexen 7450ee7f8a
Merge pull request #2203 from antmicro/fix-grammar
Signed and macro grammar update
2020-07-01 16:41:32 +02:00
..
.gitignore
const2ast.cc
Makefile.inc
preproc.cc MSVC does not understand __builtin_unreachable 2020-06-17 15:10:08 +02:00
preproc.h
verilog_frontend.cc Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
verilog_frontend.h frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
verilog_lexer.l Merge pull request #2179 from splhack/static-cast 2020-07-01 16:40:20 +02:00
verilog_parser.y Merge pull request #2203 from antmicro/fix-grammar 2020-07-01 16:41:32 +02:00