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https://github.com/YosysHQ/yosys
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65 lines
1.7 KiB
Text
65 lines
1.7 KiB
Text
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read_rtlil << EOF
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module \top
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wire input 1 \clk
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wire input 2 width 2 \addr
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wire output 1 \o
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memory size 3 offset 0 \my_array
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# potentially dangerous - requires external control to avoid illegal access
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cell $memrd \bad_rd
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parameter \MEMID "\\my_array"
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parameter \CLK_ENABLE 0
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parameter \CLK_POLARITY 1
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parameter \TRANSPARENT 0
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parameter \ABITS 2
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parameter \WIDTH 1
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connect \CLK 1'x
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connect \EN 1'x
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connect \ADDR \addr
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connect \DATA \o
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end
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wire width 2 \n_addr
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cell $not \not_addr
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parameter \A_SIGNED 0
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parameter \A_WIDTH 2
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parameter \Y_WIDTH 2
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connect \A \addr
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connect \Y \n_addr
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end
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# address is partially const, making the illegal access of 2'11 impossible
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cell $memrd \partial_const_rd
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parameter \MEMID "\\my_array"
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parameter \CLK_ENABLE 0
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parameter \CLK_POLARITY 1
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parameter \TRANSPARENT 0
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parameter \ABITS 2
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parameter \WIDTH 1
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connect \CLK 1'x
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connect \EN 1'x
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connect \ADDR { 1'0 \addr [0] }
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connect \DATA \o
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end
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# address is non-const but limited to 2'10 and 2'01 - both of which are valid
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cell $memrd \limited_rd
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parameter \MEMID "\\my_array"
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parameter \CLK_ENABLE 0
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parameter \CLK_POLARITY 1
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parameter \TRANSPARENT 0
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parameter \ABITS 2
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parameter \WIDTH 1
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connect \CLK 1'x
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connect \EN 1'x
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connect \ADDR { \n_addr [0] \addr [0] }
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connect \DATA \o
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end
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end
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EOF
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logger -expect warning "potentially dangerous non-const input \\addr" 1
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# unhandled false-positives
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# logger -werror "potentially dangerous non-const input \{ 1'0"
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# logger -werror "potentially dangerous non-const input \{ \\n_addr"
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check_mem -non-const
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logger -check-expected
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design -reset
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