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52e0030cc5
Verific reports it as 16 2-bit addresses, meaning we have to iterate over the last dimension while skipping indices.
13 lines
297 B
Systemverilog
13 lines
297 B
Systemverilog
module top;
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(* nomem2reg *)
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logic [1:0] a3 [-2:-1][-1:1] = '{'{0, 1, 2}, '{1, 0, 3}};
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always_comb begin
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assert(a3[-2][-1] == 0);
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assert(a3[-2][0] == 1);
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assert(a3[-2][1] == 2);
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assert(a3[-1][-1] == 1);
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assert(a3[-1][0] == 0);
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assert(a3[-1][1] == 3);
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end
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endmodule
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