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yosys/tests/arch/anlogic/mux.ys
2025-09-09 10:04:08 +12:00

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read_verilog ../common/mux.v
design -save read
hierarchy -top mux2
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT3
select -assert-none t:AL_MAP_LUT3 %% t:* %D
design -load read
hierarchy -top mux4
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 1 t:AL_MAP_LUT6
select -assert-none t:AL_MAP_LUT6 %% t:* %D
design -load read
hierarchy -top mux8
proc
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-max 3 t:AL_MAP_LUT3
select -assert-max 3 t:AL_MAP_LUT4
select -assert-max 1 t:AL_MAP_LUT5
select -assert-max 1 t:AL_MAP_LUT6
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t:* %D
design -load read
hierarchy -top mux16
proc
# Flaky test, started failing with statically allocated IdStrings, but works
# for me locally when I scramble the names using:
#
# rename -scramble-name -seed 1
#
#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
#design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
#cd mux16 # Constrain all select calls below inside the top module
#show
#select -assert-count 5 t:AL_MAP_LUT6
#select -assert-none t:AL_MAP_LUT6 %% t:* %D