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18 lines
321 B
Verilog
18 lines
321 B
Verilog
module top(
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input [8:0] a,
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input [8:0] b,
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output [8:0] o1,
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output [2:0] o2,
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input [2:0] c,
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input [2:0] d,
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output [2:0] o3,
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output [2:0] o4,
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input s
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);
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assign o1 = (s ? 0 : a + b);
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assign o2 = (s ? a : a - b);
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assign o3 = (s ? 4'b1111 : d + c);
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assign o4 = (s ? d : c - d);
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endmodule
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