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.gitignore
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Moved all tests in arch sub directory
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2019-10-18 11:06:12 +02:00 |
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abc9_dff.ys
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abc9_ops: update messaging (credit to @Xiretza for spotting)
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2020-05-30 08:57:48 -07:00 |
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add_sub.ys
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xilinx: Initial support for LUT4 devices.
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2020-02-07 09:03:22 +01:00 |
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adffs.ys
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Make test without iopads
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2019-12-28 16:22:24 +01:00 |
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attributes_test.ys
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Make test without iopads
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2019-12-28 16:22:24 +01:00 |
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blockram.ys
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Make test without iopads
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2019-12-28 16:22:24 +01:00 |
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bug1460.ys
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Make test without iopads
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2019-12-28 16:22:24 +01:00 |
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bug1462.ys
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xilinx_dsp: another typo; move xilinx specific test
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2020-01-17 17:07:03 -08:00 |
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bug1480.ys
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Cleanup tests
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2020-02-27 10:17:29 -08:00 |
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bug1598.ys
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Add #1598 testcase
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2019-12-27 16:44:57 -08:00 |
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bug1605.ys
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Added a test case
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2020-01-01 16:24:30 +01:00 |
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counter.ys
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Fix tests
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2020-01-10 14:48:01 +01:00 |
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dffs.ys
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abc9_ops: -reintegrate to use derived_type for box_ports
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2020-02-05 14:46:48 -08:00 |
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dsp_cascade.ys
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Fix new tests
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2019-12-28 16:43:19 +01:00 |
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dsp_fastfir.ys
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Make test without iopads
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2019-12-28 16:22:24 +01:00 |
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dsp_simd.ys
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Moved all tests in arch sub directory
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2019-10-18 11:06:12 +02:00 |
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fsm.ys
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Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"
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2020-02-27 10:17:29 -08:00 |
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latches.ys
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Make test without iopads
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2019-12-28 16:22:24 +01:00 |
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logic.ys
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Make test without iopads
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2019-12-28 16:22:24 +01:00 |
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lutram.ys
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xilinx: Add support for LUT RAM on LUT4-based devices.
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2020-02-07 09:03:22 +01:00 |
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macc.sh
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
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2019-12-22 20:51:14 +01:00 |
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macc.v
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tests: xilinx macc test to have initval, shorten BMC depth for runtime
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2020-05-25 10:09:05 -07:00 |
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macc.ys
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tests: xilinx macc test to have initval, shorten BMC depth for runtime
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2020-05-25 10:09:05 -07:00 |
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macc_tb.v
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Moved all tests in arch sub directory
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2019-10-18 11:06:12 +02:00 |
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mul.ys
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Fix new tests
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2019-12-28 16:43:19 +01:00 |
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mul_unsigned.v
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Moved all tests in arch sub directory
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2019-10-18 11:06:12 +02:00 |
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mul_unsigned.ys
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Fix new tests
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2019-12-28 16:43:19 +01:00 |
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mux.ys
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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mux_lut4.ys
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xilinx: Initial support for LUT4 devices.
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2020-02-07 09:03:22 +01:00 |
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nosrl.ys
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xilinx: Fix srl regression.
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2020-07-12 23:41:27 +02:00 |
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opt_lut_ins.ys
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Add opt_lut_ins pass. (#1673)
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2020-02-03 14:57:17 +01:00 |
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pmgen_xilinx_srl.ys
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satgen: Add support for dffe, sdff, sdffe, sdffce cells.
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2020-07-24 03:19:21 +02:00 |
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run-test.sh
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Fix path to yosys
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2019-10-18 11:12:03 +02:00 |
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shifter.ys
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Make test without iopads
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2019-12-28 16:22:24 +01:00 |
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tribuf.sh
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fix argument order for macOS compatibility
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2020-03-18 15:11:49 +01:00 |
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tribuf.ys
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Addressed review comments
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2019-12-21 20:23:23 +01:00 |
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xilinx_dffopt.ys
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xilinx: xilinx_dffopt to read cells_sim.v; fix test
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2020-04-22 16:25:23 -07:00 |
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xilinx_dffopt_blacklist.txt
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xilinx: Add xilinx_dffopt pass (#1557)
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2019-12-18 13:43:43 +01:00 |
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xilinx_dsp.ys
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tests: read +/xilinx/cell_sim.v before xilinx_dsp test
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2020-04-22 17:50:30 -07:00 |
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xilinx_srl.v
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tests: fix some test warnings
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2020-05-25 10:07:58 -07:00 |
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xilinx_srl.ys
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Moved all tests in arch sub directory
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2019-10-18 11:06:12 +02:00 |
