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yosys/techlibs/analogdevices
2025-11-14 12:08:36 +13:00
..
abc9_model.v Create synth_analogdevices 2025-11-12 22:44:11 +00:00
arith_map.v analogdevices: update timing model 2025-11-12 22:44:12 +00:00
brams.txt analogdevices: Fixup SP2_1024x18_BP 2025-11-14 10:14:36 +13:00
brams_defs.vh Create synth_analogdevices 2025-11-12 22:44:11 +00:00
brams_map.v analogdevices: Fix INIT_FILE on small mem 2025-11-14 12:08:36 +13:00
cells_map.v Create synth_analogdevices 2025-11-12 22:44:11 +00:00
cells_sim.v analogdevices: Use dump_meminit 2025-11-14 10:14:36 +13:00
dsp_map.v analogdevices: DSP inference 2025-11-12 22:44:12 +00:00
ff_map.v test suite 2025-11-12 22:44:11 +00:00
lut_map.v analogdevices: use single tech param 2025-11-12 22:44:12 +00:00
lutrams.txt analogdevices: double LUT RAM cost 2025-11-12 22:44:12 +00:00
lutrams_map.v analogdevices: Add BRAM options 2025-11-12 22:44:12 +00:00
Makefile.inc analogdevices: remove cells_xtra 2025-11-12 22:44:12 +00:00
mux_map.v Create synth_analogdevices 2025-11-12 22:44:11 +00:00
retarget_map.v analogdevices: user retargeting 2025-11-12 22:44:12 +00:00
synth_analogdevices.cc analogdevices: Use dump_meminit 2025-11-14 10:14:36 +13:00