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29 lines
647 B
Verilog
29 lines
647 B
Verilog
// Nothing to prove in this demo.
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// Just an example for memories, vcd dumps and vlog testbench dumps.
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`ifdef FORMAL
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`define assume(_expr_) assume(_expr_)
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`else
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`define assume(_expr_)
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`endif
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module demo2(input clk, input [4:0] addr, output reg [31:0] data);
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reg [31:0] mem [0:31];
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always @(negedge clk)
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data <= mem[addr];
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reg [31:0] used_addr = 0;
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reg [31:0] used_dbits = 0;
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reg initstate = 1;
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always @(posedge clk) begin
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initstate <= 0;
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`assume(!used_addr[addr]);
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used_addr[addr] <= 1;
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if (!initstate) begin
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`assume(data != 0);
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`assume((used_dbits & data) == 0);
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used_dbits <= used_dbits | data;
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end
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end
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endmodule
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