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yosys/backends/cxxrtl
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Asu dc77563a6a cxxrtl: keep the memory write queue sorted on insertion. 
Strategically inserting the pending memory write in memory::update to keep the
queue sorted allows us to skip the queue sort in memory::commit.

The Minerva SRAM SoC runs ~7% faster as a result.
2020-04-22 20:53:12 +02:00
..
cxxrtl.cc cxxrtl: run edge detectors only once in eval(). 2020-04-22 12:47:28 +00:00
cxxrtl.h cxxrtl: keep the memory write queue sorted on insertion. 2020-04-22 20:53:12 +02:00
Makefile.inc write_cxxrtl: new backend. 2020-04-09 04:08:36 +00:00