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https://github.com/YosysHQ/yosys
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43 lines
902 B
Text
43 lines
902 B
Text
design -reset
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read -vlog2k <<EOF
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module top(input clk, input a, input b, output [9:0] x);
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wire [9:0] ripple;
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reg [9:0] prev_ripple = 9'b0;
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always @(posedge clk) prev_ripple <= ripple;
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assign ripple = {ripple[8:0], a} ^ prev_ripple; // only cyclic at the coarse-grain level
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assign x = ripple[9] + b;
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endmodule
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EOF
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hierarchy -top top
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prep
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check -assert
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design -reset
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read -vlog2k <<EOF
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module top(clk, y, sideread_addr, sideread_data);
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input wire clk;
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reg [7:0] mem [255:0];
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reg [8:0] i;
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initial begin
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for (i = 0; i < 256; i = i + 1)
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mem[i] = i * 371;
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end
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output reg [7:0] y = 1;
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always @(posedge clk)
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y <= mem[y];
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input wire [7:0] sideread_addr;
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output wire [7:0] sideread_data;
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assign sideread_data = mem[sideread_addr];
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endmodule
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EOF
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hierarchy -top top
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prep -rdff
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select -assert-count 1 t:$mem_v2
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check -assert
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memory_unpack
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select -assert-count 2 t:$memrd_v2
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check -assert
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