3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-15 15:25:28 +00:00
yosys/tests/arch/xilinx
2020-03-18 15:11:49 +01:00
..
.gitignore
abc9_dff.ys Combine tests to check multiple clock domains 2020-01-02 14:38:59 -08:00
abc9_map.ys
add_sub.ys xilinx: Initial support for LUT4 devices. 2020-02-07 09:03:22 +01:00
adffs.ys
attributes_test.ys
blockram.ys
bug1460.ys
bug1462.ys xilinx_dsp: another typo; move xilinx specific test 2020-01-17 17:07:03 -08:00
bug1480.ys Cleanup tests 2020-02-27 10:17:29 -08:00
bug1598.ys
bug1605.ys Added a test case 2020-01-01 16:24:30 +01:00
counter.ys Fix tests 2020-01-10 14:48:01 +01:00
dffs.ys abc9_ops: -reintegrate to use derived_type for box_ports 2020-02-05 14:46:48 -08:00
dsp_cascade.ys
dsp_fastfir.ys
dsp_simd.ys
fsm.ys Revert "Fix tests/arch/xilinx/fsm.ys to count flops only" 2020-02-27 10:17:29 -08:00
latches.ys
logic.ys
lutram.ys xilinx: Add support for LUT RAM on LUT4-based devices. 2020-02-07 09:03:22 +01:00
macc.sh
macc.v
macc.ys
macc_tb.v
mul.ys
mul_unsigned.v
mul_unsigned.ys
mux.ys
mux_lut4.ys xilinx: Initial support for LUT4 devices. 2020-02-07 09:03:22 +01:00
opt_lut_ins.ys Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
pmgen_xilinx_srl.ys
run-test.sh
shifter.ys
tribuf.sh fix argument order for macOS compatibility 2020-03-18 15:11:49 +01:00
tribuf.ys
xilinx_dffopt.ys
xilinx_dffopt_blacklist.txt
xilinx_dsp.ys ice40_dsp: fix typo 2020-01-17 16:08:04 -08:00
xilinx_srl.v
xilinx_srl.ys