| .. |
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achronix
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techlibs: fix typo in help message
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2023-11-13 16:29:52 +13:00 |
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anlogic
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Fix some synth_* help messages
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2024-03-18 11:33:18 +13:00 |
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common
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Make all vector-size related integer params in $print sim model signed
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2025-03-25 13:08:49 +00:00 |
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coolrunner2
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Blackbox all whiteboxes after synthesis
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2021-03-17 21:07:20 +00:00 |
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easic
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Fixing old e-mail addresses and deadnames
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2021-06-08 00:39:36 +02:00 |
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ecp5
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Changing non clocked alway assignment to blocking.
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2025-04-23 16:59:53 +02:00 |
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efinix
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Merge pull request #4285 from YosysHQ/typo_fixup
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2024-04-25 09:54:48 +12:00 |
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fabulous
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Fix some synth_* help messages
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2024-03-18 11:33:18 +13:00 |
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gatemate
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gatemate: Set unused BRAM inputs to 'bx
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2025-04-28 14:42:16 +02:00 |
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gowin
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Gowin. Remove unnecessary modules
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2025-03-28 06:34:26 +10:00 |
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greenpak4
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Change to use blocking assignments in non-clocked processes.
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2025-04-23 17:21:32 +02:00 |
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ice40
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ice40_dsp: add unextend_unsigned function
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2025-04-11 19:41:35 +03:00 |
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intel
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Removed SystemVerilog module end label
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2024-03-19 01:31:36 +01:00 |
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intel_alm
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intel_alm: drop quartus support
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2024-05-03 11:32:33 +01:00 |
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lattice
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Fix some synth_* help messages
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2024-03-18 11:33:18 +13:00 |
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microchip
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pmgen: Move passes out of pmgen folder
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2025-01-31 15:18:28 +13:00 |
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nanoxplore
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Cleanup of synth_nanoxplore pass
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2024-09-03 10:15:50 +02:00 |
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nexus
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Fix some synth_* help messages
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2024-03-18 11:33:18 +13:00 |
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quicklogic
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create duplicate IOFFs if multiple output ports are connected to the same register
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2025-01-31 11:28:57 +01:00 |
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sf2
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Test fixes for latest iverilog
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2022-09-21 15:46:43 +02:00 |
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xilinx
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URAM mapping : Add test for 2048 x 144b
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2025-05-10 14:53:56 +02:00 |
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.gitignore
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pmgen: Move passes out of pmgen folder
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2025-01-31 15:18:28 +13:00 |
