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yosys/techlibs/xilinx/xc3s_mult_map.v
Miodrag Milanovic 48a3dcc02a End of file fix
2026-06-23 07:23:41 +02:00

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Verilog

module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
MULT18X18 _TECHMAP_REPLACE_ (
.A(A),
.B(B),
.P(Y)
);
endmodule