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yosys/backends/verilog
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Catherine bc9206f0f5 write_verilog: emit casez as if/elif/else whenever possible.
2024-01-09 14:49:20 +00:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc write_verilog: emit casez as if/elif/else whenever possible. 2024-01-09 14:49:20 +00:00