Maciej Kurc 1f52332b8d Added tests for Verilog frontent for attributes on parameters and localparams ... Signed-off-by: Maciej Kurc <mkurc@antmicro.com>		2019-05-16 12:53:43 +02:00
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aiger	Add tests/aiger/.gitignore	2019-04-19 14:04:12 +02:00
asicworld	Fix FIRRTL to Verilog process instance subfield assignment.	2019-02-25 16:18:13 -08:00
bram
errors
fsm
hana
liberty	Liberty file parser now accepts superfluous ;	2019-03-27 15:16:19 +01:00
lut
memories	Fix #938 - Crash occurs in case when use write_firrtl command	2019-05-01 13:16:01 -07:00
opt	Fix WREDUCE on FF not fixing ARST_VALUE parameter.	2019-02-22 10:30:42 -08:00
realmath
sat	support repeat loops with constant repeat counts outside of constant functions	2019-04-09 12:28:32 -04:00
share
simple	Added tests for Verilog frontent for attributes on parameters and localparams	2019-05-16 12:53:43 +02:00
smv
sva	Fix "verific -extnets" for more complex situations	2019-03-26 14:17:46 +01:00
svinterfaces	Fix typo in tests/svinterfaces/runone.sh	2019-05-03 14:40:51 +02:00
techmap
tools	iverilog with simcells.v as well	2019-05-03 14:03:51 -07:00
unit
various	Merge pull request #946 from YosysHQ/clifford/specify	2019-05-06 20:57:15 +02:00
vloghtb