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18 lines
337 B
Verilog
18 lines
337 B
Verilog
module signed_test01(a, b, xu, xs, yu, ys, zu, zs);
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input signed [1:0] a;
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input signed [2:0] b;
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output [3:0] xu, xs;
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output [3:0] yu, ys;
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output zu, zs;
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assign xu = (a + b) + 3'd0;
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assign xs = (a + b) + 3'sd0;
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assign yu = {a + b} + 3'd0;
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assign ys = {a + b} + 3'sd0;
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assign zu = a + b != 3'd0;
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assign zs = a + b != 3'sd0;
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endmodule
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