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20 lines
365 B
Verilog
20 lines
365 B
Verilog
module top(
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IDENT_V_,
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IDENT_W_,
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IDENT_X_,
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IDENT_Y_,
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IDENT_Z_,
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IDENT_A_,
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IDENT_B_,
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IDENT_C_
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);
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`define MACRO(dummy, x) IDENT_``x``_
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output wire IDENT_V_;
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output wire `MACRO(_,W);
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output wire `MACRO(_, X);
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output wire `MACRO(_,Y );
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output wire `MACRO(_, Z );
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output wire `MACRO(_, A);
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output wire `MACRO(_,B );
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output wire `MACRO(_, C );
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endmodule
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