Krystine Sherwin 8ded7020f4 tests: asymmetric sync rams now correctly asymmetric ... Also both use the same named parameters for better mirroring.		2023-12-04 15:52:03 +01:00
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memory_attributes	Fixing compiler warning/issues. Moving test script to the correct place	2019-12-16 10:23:45 -06:00
add_sub.v	Unify verilog style	2019-10-18 12:50:24 +02:00
adffs.v	Allow initial blocks to be disabled during tests	2021-11-13 21:53:25 +01:00
blockram.v	tests: asymmetric sync rams now correctly asymmetric	2023-12-04 15:52:03 +01:00
blockrom.v	ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.	2020-02-06 16:52:51 +00:00
counter.v	Fix files with CRLF line endings	2021-06-09 12:16:33 +02:00
dffs.v	Allow initial blocks to be disabled during tests	2021-11-13 21:53:25 +01:00
fsm.v	Fix files with CRLF line endings	2021-06-09 12:16:33 +02:00
latches.v	Unify verilog style	2019-10-18 12:50:24 +02:00
logic.v	Unify verilog style	2019-10-18 12:50:24 +02:00
lutram.v	Rename memory tests to lutram, add more xilinx tests	2019-12-12 17:44:37 -08:00
mul.v	intel_alm: Add multiply signedness to cells	2020-08-26 22:50:16 +02:00
mux.v	Unify verilog style	2019-10-18 12:50:24 +02:00
shifter.v	Allow initial blocks to be disabled during tests	2021-11-13 21:53:25 +01:00
tribuf.v	Unify verilog style	2019-10-18 12:50:24 +02:00