Clifford Wolf d0117d7d12 Merge branch 'master' into clifford/pmgen		2019-08-20 11:39:23 +02:00
..
aiger	tests: use optional ABCEXTERNAL when specified	2019-06-27 23:00:13 -04:00
arch	Add simcells.v, simlib.v, and some output	2019-06-27 11:13:49 -07:00
asicworld	Fix FIRRTL to Verilog process instance subfield assignment.	2019-02-25 16:18:13 -08:00
bram
errors	Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,	2018-10-25 02:37:56 +03:00
fsm	Speed up "make test" and related cleanups	2019-08-17 14:37:07 +02:00
hana
liberty	Liberty file parser now accepts superfluous ;	2019-03-27 15:16:19 +01:00
lut	Forgot to commit	2019-07-16 12:44:26 -07:00
memories	memory_dff: Fix checking of feedback mux input when more than one mux	2019-07-02 13:35:50 +01:00
opt	Merge remote-tracking branch 'origin/master' into clifford/testfast	2019-08-18 21:29:15 -07:00
opt_share	Support various binary operators in opt_share	2019-08-04 19:06:38 +02:00
proc	proc_clean: fix order of switch insertion.	2019-08-19 16:44:23 +00:00
realmath
sat	support repeat loops with constant repeat counts outside of constant functions	2019-04-09 12:28:32 -04:00
share
simple	Add test case for real parameters	2019-08-20 11:38:21 +02:00
simple_abc9	Add *.sv to tests/simple_abc9/.gitignore	2019-08-19 13:04:57 +02:00
smv
sva	Fix "verific -extnets" for more complex situations	2019-03-26 14:17:46 +01:00
svinterfaces	Fix typo in tests/svinterfaces/runone.sh	2019-05-03 14:40:51 +02:00
techmap	Move tests/techmap/abc9 to simple_abc9	2019-02-20 15:34:59 -08:00
tools	autotest.sh to define _AUTOTB when test_autotb	2019-06-28 14:56:22 -07:00
unit
various	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen	2019-08-19 13:04:06 +02:00
vloghtb