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24 lines
701 B
Verilog
24 lines
701 B
Verilog
module reset_test #(parameter WIDTH=256, SELW=2)
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(input clk ,
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input [9:0] ctrl ,
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input [15:0] din ,
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input [SELW-1:0] sel ,
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input wire reset,
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output reg [WIDTH-1:0] dout);
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reg [5:0] i;
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wire [SELW-1:0] rval = {reset, {SELW-1{1'b0}}};
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localparam SLICE = WIDTH/(SELW**2);
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// Doing exotic reset. masking 2 LSB bits to 0, 6 MSB bits to 1 for
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// whatever reason.
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always @(posedge clk) begin
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if (reset) begin: reset_mask
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for (i = 0; i < 16; i=i+1) begin
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dout[i*rval+:SLICE] <= 32'hDEAD;
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end
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end
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//else begin
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dout[ctrl*sel+:SLICE] <= din;
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//end
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end
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endmodule
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