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13 lines
321 B
Verilog
13 lines
321 B
Verilog
module original #(parameter WIDTH=256, SELW=2)
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(input clk ,
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input [9:0] ctrl ,
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input [15:0] din ,
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input [SELW-1:0] sel ,
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output reg [WIDTH-1:0] dout);
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localparam SLICE = WIDTH/(SELW**2);
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always @(posedge clk)
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begin
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dout[ctrl*sel+:SLICE] <= din ;
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end
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endmodule
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