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19 lines
449 B
Verilog
19 lines
449 B
Verilog
module multiple_blocking #(parameter WIDTH=256, SELW=2)
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(input clk ,
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input [9:0] ctrl ,
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input [15:0] din ,
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input [SELW-1:0] sel ,
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output reg [WIDTH:0] dout);
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localparam SLICE = WIDTH/(SELW**2);
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reg [9:0] a;
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reg [SELW-1:0] b;
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reg [15:0] c;
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always @(posedge clk) begin
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a = ctrl + 1;
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b = sel - 1;
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c = ~din;
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dout = dout + 1;
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dout[a*b+:SLICE] = c;
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end
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endmodule
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