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13 lines
482 B
Text
13 lines
482 B
Text
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read_verilog luttrees.v
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design -save read
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hierarchy -top luttrees
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proc
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equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -nomx4 -nomx8 # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd luttrees # Constrain all select calls below inside the top module
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select -assert-count 750 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %%
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select -assert-none t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D
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