mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-24 00:14:36 +00:00
Code Activity
yosys/backends/verilog
History
Jannis Harder 79e05a195d verilog: Bufnorm cell backend and frontend support 
This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
2025-09-17 14:01:09 +02:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc verilog: Bufnorm cell backend and frontend support 2025-09-17 14:01:09 +02:00
verilog_backend.h rename: add -unescape 2025-06-24 12:33:33 +02:00