mirror of
https://github.com/YosysHQ/yosys
synced 2025-05-14 19:24:45 +00:00
126 lines
3.5 KiB
C++
126 lines
3.5 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/rtlil.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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PRIVATE_NAMESPACE_BEGIN
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USING_YOSYS_NAMESPACE
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// promote dspv2_16x9x32_cfg_ports to dspv2_32x18x64_cfg_ports if need be
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bool promote(Module *m, Cell *cell) {
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if (cell->type == ID(dspv2_32x18x64_cfg_ports)) {
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return false;
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} else {
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log_assert(cell->type == ID(dspv2_16x9x32_cfg_ports));
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}
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auto widen_output = [&](IdString port_name, int new_width) {
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if (!cell->hasPort(port_name))
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return;
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SigSpec port = cell->getPort(port_name);
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if (port.size() < new_width) {
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port = {m->addWire(NEW_ID, new_width - port.size()), port};
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cell->setPort(port_name, port);
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}
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};
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auto widen_input = [&](IdString port_name, int new_width) {
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if (!cell->hasPort(port_name))
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return;
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SigSpec port = cell->getPort(port_name);
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if (port.size() < new_width) {
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port.extend_u0(new_width, /* is_signed= */ true);
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cell->setPort(port_name, port);
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}
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};
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widen_output(ID(z_o), 50);
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widen_output(ID(a_cout_o), 32);
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widen_output(ID(b_cout_o), 18);
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widen_output(ID(z_cout_o), 50);
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auto uses_port = [&](IdString port_name) {
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return cell->hasPort(port_name) && !cell->getPort(port_name).is_fully_undef();
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};
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if (uses_port(ID(a_cin_i)) || uses_port(ID(b_cin_i)) || uses_port(ID(z_cin_i))) {
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log_error("Cannot promote %s (type %s) with cascading paths\n", log_id(cell), log_id(cell->type));
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}
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widen_input(ID(a_i), 32);
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widen_input(ID(b_i), 18);
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widen_input(ID(c_i), 18);
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cell->type = ID(dspv2_32x18x64_cfg_ports);
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return true;
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}
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bool did_something;
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#include "ql_dsp_pm.h"
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struct QlDspPass : Pass {
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QlDspPass() : Pass("ql_dsp", "pack into QuickLogic DSPs") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ql_dsp [selection]\n");
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log("\n");
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log("This pass packs input and output path registers into QuickLogic DSP blocks,\n");
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log("additionally it supports Z path cascading and post-adder packing.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *d) override
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{
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log_header(d, "Executing QL_DSP pass. (pack into QuickLogic DSPs)\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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break;
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}
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extra_args(args, argidx, d);
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for (auto module : d->selected_modules()) {
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did_something = true;
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while (did_something)
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{
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// TODO: could be optimized by more reuse of the pmgen object
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did_something = false;
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{
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ql_dsp_pm pm(module, module->selected_cells());
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pm.run_ql_dsp_pack_regs();
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}
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{
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ql_dsp_pm pm(module, module->selected_cells());
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pm.run_ql_dsp_cascade();
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}
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{
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ql_dsp_pm pm(module, module->selected_cells());
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pm.run_ql_dsp_pack_regs();
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}
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}
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}
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}
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} QlDspPass;
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PRIVATE_NAMESPACE_END
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