mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-30 01:48:47 +00:00
Code Activity
yosys/techlibs/gowin
History
YRabbit c37db637c7 Gowin. Remove unnecessary modules 
Primitives that are not planned for implementation for reasons of
belonging to old unsupported chips or representing composite complex IPs
rather than primitives are removed.
Also latches and large MUXes not planned for implementation.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
2025-03-28 06:34:26 +10:00
..
arith_map.v
brams.txt
brams_map.v
cells_map.v
cells_sim.v Update ALU MULT mode in gowin to match nextpnr 2024-12-23 11:12:48 +01:00
cells_xtra.py Gowin. Remove unnecessary modules 2025-03-28 06:34:26 +10:00
cells_xtra_gw1n.v Gowin. Remove unnecessary modules 2025-03-28 06:34:26 +10:00
cells_xtra_gw2a.v Gowin. Remove unnecessary modules 2025-03-28 06:34:26 +10:00
cells_xtra_gw5a.v Gowin. Remove unnecessary modules 2025-03-28 06:34:26 +10:00
lutrams.txt
lutrams_map.v
Makefile.inc gowin: split cells_xtra by family 2024-11-26 15:42:22 +01:00
synth_gowin.cc gowin: split cells_xtra by family 2024-11-26 15:42:22 +01:00