mirror of
https://github.com/YosysHQ/yosys
synced 2026-05-25 19:36:21 +00:00
20 lines
728 B
Text
20 lines
728 B
Text
# Issue #4402: read_verilog doesn't respect signed keyword
|
|
#
|
|
# write_verilog drops the signed keyword from input port declarations,
|
|
# even though the internal comparison logic is correctly preserved via
|
|
# explicit $signed() casts. The port declaration should retain signed
|
|
# so that the interface contract is correct for downstream tools.
|
|
|
|
! mkdir -p temp
|
|
|
|
read_verilog <<EOT
|
|
module mod (output k, input signed [5:0] wire0);
|
|
assign k = (wire0 <= 0);
|
|
endmodule
|
|
EOT
|
|
hierarchy -top mod
|
|
write_verilog temp/issue4402_roundtrip.v
|
|
|
|
# The output port declaration must include the signed keyword.
|
|
# Bug: write_verilog emits `input [5:0] wire0` instead of `input signed [5:0] wire0`.
|
|
! grep -q "input signed" temp/issue4402_roundtrip.v
|