Charlotte 4e94f62116 simlib: blackbox $print cell ... It's possible to `generate` the appropriate always blocks per the triggers, but unlikely to be worth parsing the RTLIL \FORMAT parameter.		2023-08-11 04:46:52 +02:00
..
.gitignore
abc9_map.v
abc9_model.v
abc9_unmap.v
adff2dff.v
cellhelp.py
cells.lib
cmp2lcu.v
cmp2lut.v
dff2ff.v
gate2lut.v
gen_fine_ffs.py
Makefile.inc
mul2dsp.v
pmux2mux.v
prep.cc
simcells.v
simlib.v	simlib: blackbox $print cell	2023-08-11 04:46:52 +02:00
smtmap.v
synth.cc
techmap.v