Clifford Wolf dbfd8460a9 Allow $size and $bits in verilog mode, actually check test case		2017-09-29 11:56:43 +02:00
..
.gitignore
asserts.v
asserts.ys
asserts_seq.v
asserts_seq.ys
counters.v
counters.ys
expose_dff.v
expose_dff.ys
initval.v
initval.ys
run-test.sh
share.v
share.ys
sizebits.sv
sizebits.ys
splice.v
splice.ys