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28 lines
487 B
Text
28 lines
487 B
Text
read_verilog -specify <<EOT
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module top(input a, b, output o);
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assign o = a & b;
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endmodule
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(* blackbox *)
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module bb(input a, b, output o);
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assign o = a | b;
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specify
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(a => o) = 1;
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endspecify
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endmodule
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(* whitebox *)
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module wb(input a, b, output o);
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assign o = a ^ b;
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endmodule
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EOT
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clean
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select -assert-count 1 c:*
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select -assert-none t:* t:$and %d
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select -assert-count 3 w:*
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select -assert-count 4 *
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select -assert-count 3 =c:*
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select -assert-count 10 =w:*
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select -assert-count 13 =*
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