mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 17:44:09 +00:00
4e70c30775
- FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
89 lines
2.6 KiB
C++
89 lines
2.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/ffinit.h"
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#include "kernel/ff.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct ZinitPass : public Pass {
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ZinitPass() : Pass("zinit", "add inverters so all FF are zero-initialized") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" zinit [options] [selection]\n");
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log("\n");
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log("Add inverters as needed to make all FFs zero-initialized.\n");
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log("\n");
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log(" -all\n");
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log(" also add zero initialization to uninitialized FFs\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool all_mode = false;
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log_header(design, "Executing ZINIT pass (make all FFs zero-initialized).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-all") {
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all_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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FfInitVals initvals(&sigmap, module);
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for (auto cell : module->selected_cells())
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{
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if (!RTLIL::builtin_ff_cell_types().count(cell->type))
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continue;
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FfData ff(&initvals, cell);
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log("FF init value for cell %s (%s): %s = %s\n", log_id(cell), log_id(cell->type),
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log_signal(ff.sig_q), log_signal(ff.val_init));
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pool<int> bits;
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for (int i = 0; i < ff.width; i++) {
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if (ff.val_init.bits[i] == State::S1)
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bits.insert(i);
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else if (ff.val_init.bits[i] != State::S0 && all_mode)
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ff.val_init.bits[i] = State::S0;
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}
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ff.flip_bits(bits);
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ff.emit();
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}
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}
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}
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} ZinitPass;
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PRIVATE_NAMESPACE_END
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