mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 17:44:09 +00:00
4e70c30775
- FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
484 lines
16 KiB
C++
484 lines
16 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "simplemap.h"
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#include "kernel/sigtools.h"
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#include "kernel/ff.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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USING_YOSYS_NAMESPACE
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YOSYS_NAMESPACE_BEGIN
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void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort(ID::A);
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RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
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sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
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gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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gate->setPort(ID::A, sig_a[i]);
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gate->setPort(ID::Y, sig_y[i]);
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}
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}
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void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort(ID::A);
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RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
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sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
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module->connect(RTLIL::SigSig(sig_y, sig_a));
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}
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void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort(ID::A);
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RTLIL::SigSpec sig_b = cell->getPort(ID::B);
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RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
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sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
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sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool());
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if (cell->type == ID($xnor))
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{
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y));
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
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gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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gate->setPort(ID::A, sig_t[i]);
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gate->setPort(ID::Y, sig_y[i]);
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}
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sig_y = sig_t;
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}
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IdString gate_type;
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if (cell->type == ID($and)) gate_type = ID($_AND_);
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if (cell->type == ID($or)) gate_type = ID($_OR_);
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if (cell->type == ID($xor)) gate_type = ID($_XOR_);
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if (cell->type == ID($xnor)) gate_type = ID($_XOR_);
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log_assert(!gate_type.empty());
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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gate->setPort(ID::A, sig_a[i]);
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gate->setPort(ID::B, sig_b[i]);
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gate->setPort(ID::Y, sig_y[i]);
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}
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}
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void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort(ID::A);
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RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
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if (sig_y.size() == 0)
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return;
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if (sig_a.size() == 0) {
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if (cell->type == ID($reduce_and)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
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if (cell->type == ID($reduce_or)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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if (cell->type == ID($reduce_xor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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if (cell->type == ID($reduce_xnor)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.size())));
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if (cell->type == ID($reduce_bool)) module->connect(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.size())));
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return;
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}
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if (sig_y.size() > 1) {
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module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
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sig_y = sig_y.extract(0, 1);
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}
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IdString gate_type;
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if (cell->type == ID($reduce_and)) gate_type = ID($_AND_);
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if (cell->type == ID($reduce_or)) gate_type = ID($_OR_);
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if (cell->type == ID($reduce_xor)) gate_type = ID($_XOR_);
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if (cell->type == ID($reduce_xnor)) gate_type = ID($_XOR_);
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if (cell->type == ID($reduce_bool)) gate_type = ID($_OR_);
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log_assert(!gate_type.empty());
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RTLIL::Cell *last_output_cell = NULL;
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while (sig_a.size() > 1)
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{
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2);
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for (int i = 0; i < sig_a.size(); i += 2)
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{
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if (i+1 == sig_a.size()) {
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sig_t.append(sig_a[i]);
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continue;
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}
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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gate->setPort(ID::A, sig_a[i]);
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gate->setPort(ID::B, sig_a[i+1]);
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gate->setPort(ID::Y, sig_t[i/2]);
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last_output_cell = gate;
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}
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sig_a = sig_t;
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}
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if (cell->type == ID($reduce_xnor)) {
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
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gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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gate->setPort(ID::A, sig_a);
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gate->setPort(ID::Y, sig_t);
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last_output_cell = gate;
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sig_a = sig_t;
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}
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if (last_output_cell == NULL) {
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module->connect(RTLIL::SigSig(sig_y, sig_a));
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} else {
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last_output_cell->setPort(ID::Y, sig_y);
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}
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}
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static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell *cell)
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{
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while (sig.size() > 1)
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{
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RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2);
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for (int i = 0; i < sig.size(); i += 2)
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{
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if (i+1 == sig.size()) {
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sig_t.append(sig[i]);
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continue;
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}
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_));
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gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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gate->setPort(ID::A, sig[i]);
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gate->setPort(ID::B, sig[i+1]);
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gate->setPort(ID::Y, sig_t[i/2]);
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}
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sig = sig_t;
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}
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if (sig.size() == 0)
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sig = State::S0;
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}
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void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort(ID::A);
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logic_reduce(module, sig_a, cell);
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RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
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if (sig_y.size() == 0)
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return;
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if (sig_y.size() > 1) {
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module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
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sig_y = sig_y.extract(0, 1);
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}
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
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gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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gate->setPort(ID::A, sig_a);
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gate->setPort(ID::Y, sig_y);
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}
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void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort(ID::A);
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logic_reduce(module, sig_a, cell);
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RTLIL::SigSpec sig_b = cell->getPort(ID::B);
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logic_reduce(module, sig_b, cell);
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RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
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if (sig_y.size() == 0)
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return;
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if (sig_y.size() > 1) {
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module->connect(RTLIL::SigSig(sig_y.extract(1, sig_y.size()-1), RTLIL::SigSpec(0, sig_y.size()-1)));
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sig_y = sig_y.extract(0, 1);
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}
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IdString gate_type;
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if (cell->type == ID($logic_and)) gate_type = ID($_AND_);
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if (cell->type == ID($logic_or)) gate_type = ID($_OR_);
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log_assert(!gate_type.empty());
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RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
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gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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gate->setPort(ID::A, sig_a);
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gate->setPort(ID::B, sig_b);
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gate->setPort(ID::Y, sig_y);
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}
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void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort(ID::A);
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RTLIL::SigSpec sig_b = cell->getPort(ID::B);
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RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
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bool is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
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bool is_ne = cell->type.in(ID($ne), ID($nex));
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RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
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RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
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xor_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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simplemap_bitop(module, xor_cell);
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module->remove(xor_cell);
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RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
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RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
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reduce_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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simplemap_reduce(module, reduce_cell);
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module->remove(reduce_cell);
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if (!is_ne) {
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RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y);
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not_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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simplemap_lognot(module, not_cell);
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module->remove(not_cell);
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}
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}
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void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort(ID::A);
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RTLIL::SigSpec sig_b = cell->getPort(ID::B);
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RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
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gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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gate->setPort(ID::A, sig_a[i]);
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gate->setPort(ID::B, sig_b[i]);
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gate->setPort(ID::S, cell->getPort(ID::S));
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gate->setPort(ID::Y, sig_y[i]);
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}
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}
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void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = cell->getPort(ID::A);
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RTLIL::SigSpec sig_e = cell->getPort(ID::EN);
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RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
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for (int i = 0; i < GetSize(sig_y); i++) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_));
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gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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gate->setPort(ID::A, sig_a[i]);
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gate->setPort(ID::E, sig_e);
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gate->setPort(ID::Y, sig_y[i]);
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}
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}
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void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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SigSpec lut_ctrl = cell->getPort(ID::A);
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SigSpec lut_data = cell->getParam(ID::LUT);
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lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int());
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for (int idx = 0; GetSize(lut_data) > 1; idx++) {
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SigSpec sig_s = lut_ctrl[idx];
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SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
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for (int i = 0; i < GetSize(lut_data); i += 2) {
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RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
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gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
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gate->setPort(ID::A, lut_data[i]);
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gate->setPort(ID::B, lut_data[i+1]);
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gate->setPort(ID::S, lut_ctrl[idx]);
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gate->setPort(ID::Y, new_lut_data[i/2]);
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}
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lut_data = new_lut_data;
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}
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module->connect(cell->getPort(ID::Y), lut_data);
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}
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void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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SigSpec ctrl = cell->getPort(ID::A);
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SigSpec table = cell->getParam(ID::TABLE);
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int width = cell->getParam(ID::WIDTH).as_int();
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int depth = cell->getParam(ID::DEPTH).as_int();
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table.extend_u0(2 * width * depth);
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SigSpec products;
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for (int i = 0; i < depth; i++) {
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SigSpec in, pat;
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for (int j = 0; j < width; j++) {
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if (table[2*i*width + 2*j + 0] == State::S1) {
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in.append(ctrl[j]);
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pat.append(State::S0);
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}
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if (table[2*i*width + 2*j + 1] == State::S1) {
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in.append(ctrl[j]);
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pat.append(State::S1);
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}
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}
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products.append(GetSize(in) > 0 ? module->Eq(NEW_ID, in, pat) : State::S1);
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}
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module->connect(cell->getPort(ID::Y), module->ReduceOr(NEW_ID, products));
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}
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void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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int offset = cell->parameters.at(ID::OFFSET).as_int();
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RTLIL::SigSpec sig_a = cell->getPort(ID::A);
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RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
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module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
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}
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void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_ab = cell->getPort(ID::A);
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sig_ab.append(cell->getPort(ID::B));
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RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
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module->connect(RTLIL::SigSig(sig_y, sig_ab));
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}
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void simplemap_ff(RTLIL::Module *, RTLIL::Cell *cell)
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{
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FfData ff(nullptr, cell);
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for (int i = 0; i < ff.width; i++) {
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FfData fff = ff.slice({i});
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fff.is_fine = true;
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fff.emit();
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}
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}
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void simplemap_get_mappers(dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
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{
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mappers[ID($not)] = simplemap_not;
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mappers[ID($pos)] = simplemap_pos;
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mappers[ID($and)] = simplemap_bitop;
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mappers[ID($or)] = simplemap_bitop;
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mappers[ID($xor)] = simplemap_bitop;
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mappers[ID($xnor)] = simplemap_bitop;
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mappers[ID($reduce_and)] = simplemap_reduce;
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mappers[ID($reduce_or)] = simplemap_reduce;
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mappers[ID($reduce_xor)] = simplemap_reduce;
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mappers[ID($reduce_xnor)] = simplemap_reduce;
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mappers[ID($reduce_bool)] = simplemap_reduce;
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mappers[ID($logic_not)] = simplemap_lognot;
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mappers[ID($logic_and)] = simplemap_logbin;
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mappers[ID($logic_or)] = simplemap_logbin;
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mappers[ID($eq)] = simplemap_eqne;
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mappers[ID($eqx)] = simplemap_eqne;
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mappers[ID($ne)] = simplemap_eqne;
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mappers[ID($nex)] = simplemap_eqne;
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mappers[ID($mux)] = simplemap_mux;
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mappers[ID($tribuf)] = simplemap_tribuf;
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mappers[ID($lut)] = simplemap_lut;
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mappers[ID($sop)] = simplemap_sop;
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mappers[ID($slice)] = simplemap_slice;
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mappers[ID($concat)] = simplemap_concat;
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mappers[ID($sr)] = simplemap_ff;
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mappers[ID($ff)] = simplemap_ff;
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mappers[ID($dff)] = simplemap_ff;
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mappers[ID($dffe)] = simplemap_ff;
|
|
mappers[ID($dffsr)] = simplemap_ff;
|
|
mappers[ID($dffsre)] = simplemap_ff;
|
|
mappers[ID($adff)] = simplemap_ff;
|
|
mappers[ID($sdff)] = simplemap_ff;
|
|
mappers[ID($adffe)] = simplemap_ff;
|
|
mappers[ID($sdffe)] = simplemap_ff;
|
|
mappers[ID($sdffce)] = simplemap_ff;
|
|
mappers[ID($aldff)] = simplemap_ff;
|
|
mappers[ID($aldffe)] = simplemap_ff;
|
|
mappers[ID($dlatch)] = simplemap_ff;
|
|
mappers[ID($adlatch)] = simplemap_ff;
|
|
mappers[ID($dlatchsr)] = simplemap_ff;
|
|
}
|
|
|
|
void simplemap(RTLIL::Module *module, RTLIL::Cell *cell)
|
|
{
|
|
static dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
|
|
static bool initialized_mappers = false;
|
|
|
|
if (!initialized_mappers) {
|
|
simplemap_get_mappers(mappers);
|
|
initialized_mappers = true;
|
|
}
|
|
|
|
mappers.at(cell->type)(module, cell);
|
|
}
|
|
|
|
YOSYS_NAMESPACE_END
|
|
PRIVATE_NAMESPACE_BEGIN
|
|
|
|
struct SimplemapPass : public Pass {
|
|
SimplemapPass() : Pass("simplemap", "mapping simple coarse-grain cells") { }
|
|
void help() override
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" simplemap [selection]\n");
|
|
log("\n");
|
|
log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n");
|
|
log("primitives. The following internal cell types are mapped by this pass:\n");
|
|
log("\n");
|
|
log(" $not, $pos, $and, $or, $xor, $xnor\n");
|
|
log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
|
|
log(" $logic_not, $logic_and, $logic_or, $mux, $tribuf\n");
|
|
log(" $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $aldff, $aldffe, $sdff, $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n");
|
|
log("\n");
|
|
}
|
|
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
|
{
|
|
log_header(design, "Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
|
|
extra_args(args, 1, design);
|
|
|
|
dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
|
|
simplemap_get_mappers(mappers);
|
|
|
|
for (auto mod : design->modules()) {
|
|
if (!design->selected(mod) || mod->get_blackbox_attribute())
|
|
continue;
|
|
std::vector<RTLIL::Cell*> cells = mod->cells();
|
|
for (auto cell : cells) {
|
|
if (mappers.count(cell->type) == 0)
|
|
continue;
|
|
if (!design->selected(mod, cell))
|
|
continue;
|
|
log("Mapping %s.%s (%s).\n", log_id(mod), log_id(cell), log_id(cell->type));
|
|
mappers.at(cell->type)(mod, cell);
|
|
mod->remove(cell);
|
|
}
|
|
}
|
|
}
|
|
} SimplemapPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|