mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 17:44:09 +00:00
4e70c30775
- FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
107 lines
3 KiB
C++
107 lines
3 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2020 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/ff.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct DffunmapPass : public Pass {
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DffunmapPass() : Pass("dffunmap", "unmap clock enable and synchronous reset from FFs") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" dffunmap [options] [selection]\n");
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log("\n");
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log("This pass transforms FF types with clock enable and/or synchronous reset into\n");
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log("their base type (with neither clock enable nor sync reset) by emulating the clock\n");
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log("enable and synchronous reset with multiplexers on the cell input.\n");
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log("\n");
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log(" -ce-only\n");
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log(" unmap only clock enables, leave synchronous resets alone.\n");
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log("\n");
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log(" -srst-only\n");
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log(" unmap only synchronous resets, leave clock enables alone.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing DFFUNMAP pass (unmap clock enable and synchronous reset from FFs).\n");
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bool ce_only = false;
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bool srst_only = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-ce-only") {
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ce_only = true;
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continue;
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}
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if (args[argidx] == "-srst-only") {
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srst_only = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (ce_only && srst_only)
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log_cmd_error("Options -ce-only and -srst-only are mutually exclusive!\n");
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for (auto mod : design->selected_modules())
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{
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SigMap sigmap(mod);
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FfInitVals initvals(&sigmap, mod);
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for (auto cell : mod->selected_cells())
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{
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if (!RTLIL::builtin_ff_cell_types().count(cell->type))
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continue;
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FfData ff(&initvals, cell);
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IdString name = cell->name;
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if (!ff.has_clk)
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continue;
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if (ce_only) {
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if (!ff.has_ce)
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continue;
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ff.unmap_ce();
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} else if (srst_only) {
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if (!ff.has_srst)
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continue;
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ff.unmap_srst();
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} else {
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if (!ff.has_ce && !ff.has_srst)
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continue;
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ff.unmap_ce_srst();
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}
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ff.emit();
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}
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}
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}
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} DffunmapPass;
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PRIVATE_NAMESPACE_END
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