mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 17:44:09 +00:00
4e70c30775
- FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
360 lines
9.7 KiB
C++
360 lines
9.7 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/ffmerge.h"
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USING_YOSYS_NAMESPACE
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bool FfMergeHelper::is_output_unused(RTLIL::SigSpec sig) {
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for (auto bit : (*sigmap)(sig))
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if (sigbit_users_count[bit] != 0)
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return false;
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return true;
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}
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bool FfMergeHelper::find_output_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits) {
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ff = FfData(module, initvals, NEW_ID);
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sigmap->apply(sig);
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bool found = false;
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for (auto bit : sig)
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{
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if (bit.wire == NULL || sigbit_users_count[bit] == 0) {
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ff.width++;
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ff.sig_q.append(bit);
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ff.sig_d.append(bit);
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ff.sig_clr.append(State::Sx);
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ff.sig_set.append(State::Sx);
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ff.val_init.bits.push_back(State::Sx);
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ff.val_srst.bits.push_back(State::Sx);
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ff.val_arst.bits.push_back(State::Sx);
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continue;
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}
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if (sigbit_users_count[bit] != 1)
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return false;
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auto &sinks = dff_sink[bit];
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if (sinks.size() != 1)
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return false;
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Cell *cell;
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int idx;
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std::tie(cell, idx) = *sinks.begin();
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bits.insert(std::make_pair(cell, idx));
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FfData cur_ff(initvals, cell);
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// Reject latches and $ff.
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if (!cur_ff.has_clk)
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return false;
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log_assert((*sigmap)(cur_ff.sig_d[idx]) == bit);
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if (!found) {
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ff.sig_clk = cur_ff.sig_clk;
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ff.sig_ce = cur_ff.sig_ce;
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ff.sig_aload = cur_ff.sig_aload;
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ff.sig_srst = cur_ff.sig_srst;
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ff.sig_arst = cur_ff.sig_arst;
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ff.has_clk = cur_ff.has_clk;
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ff.has_ce = cur_ff.has_ce;
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ff.has_aload = cur_ff.has_aload;
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ff.has_srst = cur_ff.has_srst;
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ff.has_arst = cur_ff.has_arst;
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ff.has_sr = cur_ff.has_sr;
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ff.ce_over_srst = cur_ff.ce_over_srst;
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ff.pol_clk = cur_ff.pol_clk;
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ff.pol_ce = cur_ff.pol_ce;
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ff.pol_aload = cur_ff.pol_aload;
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ff.pol_arst = cur_ff.pol_arst;
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ff.pol_srst = cur_ff.pol_srst;
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ff.pol_clr = cur_ff.pol_clr;
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ff.pol_set = cur_ff.pol_set;
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} else {
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if (ff.has_clk != cur_ff.has_clk)
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return false;
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if (ff.has_ce != cur_ff.has_ce)
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return false;
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if (ff.has_aload != cur_ff.has_aload)
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return false;
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if (ff.has_srst != cur_ff.has_srst)
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return false;
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if (ff.has_arst != cur_ff.has_arst)
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return false;
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if (ff.has_sr != cur_ff.has_sr)
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return false;
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if (ff.has_clk) {
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if (ff.sig_clk != cur_ff.sig_clk)
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return false;
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if (ff.pol_clk != cur_ff.pol_clk)
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return false;
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}
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if (ff.has_ce) {
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if (ff.sig_ce != cur_ff.sig_ce)
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return false;
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if (ff.pol_ce != cur_ff.pol_ce)
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return false;
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}
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if (ff.has_aload) {
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if (ff.sig_aload != cur_ff.sig_aload)
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return false;
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if (ff.pol_aload != cur_ff.pol_aload)
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return false;
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}
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if (ff.has_srst) {
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if (ff.sig_srst != cur_ff.sig_srst)
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return false;
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if (ff.pol_srst != cur_ff.pol_srst)
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return false;
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if (ff.has_ce && ff.ce_over_srst != cur_ff.ce_over_srst)
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return false;
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}
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if (ff.has_arst) {
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if (ff.sig_arst != cur_ff.sig_arst)
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return false;
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if (ff.pol_arst != cur_ff.pol_arst)
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return false;
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}
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if (ff.has_sr) {
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if (ff.pol_clr != cur_ff.pol_clr)
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return false;
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if (ff.pol_set != cur_ff.pol_set)
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return false;
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}
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}
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ff.width++;
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ff.sig_d.append(cur_ff.sig_d[idx]);
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ff.sig_ad.append(ff.has_aload ? cur_ff.sig_ad[idx] : State::Sx);
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ff.sig_q.append(cur_ff.sig_q[idx]);
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ff.sig_clr.append(ff.has_sr ? cur_ff.sig_clr[idx] : State::S0);
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ff.sig_set.append(ff.has_sr ? cur_ff.sig_set[idx] : State::S0);
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ff.val_arst.bits.push_back(ff.has_arst ? cur_ff.val_arst[idx] : State::Sx);
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ff.val_srst.bits.push_back(ff.has_srst ? cur_ff.val_srst[idx] : State::Sx);
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ff.val_init.bits.push_back(cur_ff.val_init[idx]);
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found = true;
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}
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return found;
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}
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bool FfMergeHelper::find_input_ff(RTLIL::SigSpec sig, FfData &ff, pool<std::pair<Cell *, int>> &bits) {
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ff = FfData();
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sigmap->apply(sig);
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bool found = false;
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pool<int> const_bits;
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for (auto bit : sig)
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{
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if (bit.wire == NULL) {
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const_bits.insert(ff.width);
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ff.width++;
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ff.sig_q.append(bit);
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ff.sig_d.append(bit);
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// These two will be fixed up later.
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ff.sig_clr.append(State::Sx);
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ff.sig_set.append(State::Sx);
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ff.val_init.bits.push_back(bit.data);
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ff.val_srst.bits.push_back(bit.data);
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ff.val_arst.bits.push_back(bit.data);
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continue;
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}
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if (!dff_driver.count(bit))
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return false;
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Cell *cell;
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int idx;
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std::tie(cell, idx) = dff_driver[bit];
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bits.insert(std::make_pair(cell, idx));
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FfData cur_ff(initvals, cell);
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log_assert((*sigmap)(cur_ff.sig_q[idx]) == bit);
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if (!found) {
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ff.sig_clk = cur_ff.sig_clk;
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ff.sig_ce = cur_ff.sig_ce;
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ff.sig_aload = cur_ff.sig_aload;
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ff.sig_srst = cur_ff.sig_srst;
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ff.sig_arst = cur_ff.sig_arst;
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ff.has_clk = cur_ff.has_clk;
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ff.has_gclk = cur_ff.has_gclk;
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ff.has_ce = cur_ff.has_ce;
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ff.has_aload = cur_ff.has_aload;
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ff.has_srst = cur_ff.has_srst;
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ff.has_arst = cur_ff.has_arst;
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ff.has_sr = cur_ff.has_sr;
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ff.ce_over_srst = cur_ff.ce_over_srst;
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ff.pol_clk = cur_ff.pol_clk;
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ff.pol_ce = cur_ff.pol_ce;
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ff.pol_aload = cur_ff.pol_aload;
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ff.pol_arst = cur_ff.pol_arst;
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ff.pol_srst = cur_ff.pol_srst;
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ff.pol_clr = cur_ff.pol_clr;
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ff.pol_set = cur_ff.pol_set;
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} else {
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if (ff.has_gclk != cur_ff.has_gclk)
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return false;
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if (ff.has_clk != cur_ff.has_clk)
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return false;
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if (ff.has_ce != cur_ff.has_ce)
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return false;
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if (ff.has_aload != cur_ff.has_aload)
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return false;
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if (ff.has_srst != cur_ff.has_srst)
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return false;
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if (ff.has_arst != cur_ff.has_arst)
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return false;
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if (ff.has_sr != cur_ff.has_sr)
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return false;
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if (ff.has_clk) {
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if (ff.sig_clk != cur_ff.sig_clk)
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return false;
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if (ff.pol_clk != cur_ff.pol_clk)
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return false;
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}
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if (ff.has_ce) {
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if (ff.sig_ce != cur_ff.sig_ce)
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return false;
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if (ff.pol_ce != cur_ff.pol_ce)
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return false;
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}
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if (ff.has_aload) {
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if (ff.sig_aload != cur_ff.sig_aload)
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return false;
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if (ff.pol_aload != cur_ff.pol_aload)
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return false;
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}
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if (ff.has_srst) {
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if (ff.sig_srst != cur_ff.sig_srst)
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return false;
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if (ff.pol_srst != cur_ff.pol_srst)
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return false;
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if (ff.has_ce && ff.ce_over_srst != cur_ff.ce_over_srst)
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return false;
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}
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if (ff.has_arst) {
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if (ff.sig_arst != cur_ff.sig_arst)
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return false;
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if (ff.pol_arst != cur_ff.pol_arst)
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return false;
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}
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if (ff.has_sr) {
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if (ff.pol_clr != cur_ff.pol_clr)
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return false;
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if (ff.pol_set != cur_ff.pol_set)
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return false;
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}
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}
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ff.width++;
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ff.sig_d.append((ff.has_clk || ff.has_gclk) ? cur_ff.sig_d[idx] : State::Sx);
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ff.sig_ad.append(ff.has_aload ? cur_ff.sig_ad[idx] : State::Sx);
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ff.sig_q.append(cur_ff.sig_q[idx]);
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ff.sig_clr.append(ff.has_sr ? cur_ff.sig_clr[idx] : State::S0);
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ff.sig_set.append(ff.has_sr ? cur_ff.sig_set[idx] : State::S0);
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ff.val_arst.bits.push_back(ff.has_arst ? cur_ff.val_arst[idx] : State::Sx);
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ff.val_srst.bits.push_back(ff.has_srst ? cur_ff.val_srst[idx] : State::Sx);
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ff.val_init.bits.push_back(cur_ff.val_init[idx]);
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found = true;
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}
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if (found && ff.has_sr) {
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for (auto i: const_bits) {
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if (ff.sig_d[i] == State::S0) {
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ff.sig_set[i] = ff.pol_set ? State::S0 : State::S1;
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} else if (ff.sig_d[i] == State::S1) {
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ff.sig_clr[i] = ff.pol_clr ? State::S0 : State::S1;
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}
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}
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}
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return found;
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}
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void FfMergeHelper::remove_output_ff(const pool<std::pair<Cell *, int>> &bits) {
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for (auto &it : bits) {
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Cell *cell = it.first;
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int idx = it.second;
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SigSpec q = cell->getPort(ID::Q);
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initvals->remove_init(q[idx]);
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dff_driver.erase((*sigmap)(q[idx]));
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q[idx] = module->addWire(stringf("$ffmerge_disconnected$%d", autoidx++));
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cell->setPort(ID::Q, q);
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}
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}
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void FfMergeHelper::mark_input_ff(const pool<std::pair<Cell *, int>> &bits) {
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for (auto &it : bits) {
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Cell *cell = it.first;
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int idx = it.second;
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if (cell->hasPort(ID::D)) {
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SigSpec d = cell->getPort(ID::D);
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// The user count was already at least 1
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// (for the D port). Bump it as it is now connected
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// to the merged-to cell as well. This suffices for
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// it to not be considered for output merging.
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sigbit_users_count[d[idx]]++;
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}
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}
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}
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void FfMergeHelper::set(FfInitVals *initvals_, RTLIL::Module *module_)
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{
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clear();
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initvals = initvals_;
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sigmap = initvals->sigmap;
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module = module_;
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for (auto wire : module->wires()) {
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if (wire->port_output)
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for (auto bit : (*sigmap)(wire))
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sigbit_users_count[bit]++;
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}
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for (auto cell : module->cells()) {
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if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
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if (cell->hasPort(ID::D)) {
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SigSpec d = (*sigmap)(cell->getPort(ID::D));
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for (int i = 0; i < GetSize(d); i++)
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dff_sink[d[i]].insert(std::make_pair(cell, i));
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}
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SigSpec q = (*sigmap)(cell->getPort(ID::Q));
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for (int i = 0; i < GetSize(q); i++)
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dff_driver[q[i]] = std::make_pair(cell, i);
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}
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for (auto &conn : cell->connections())
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if (!cell->known() || cell->input(conn.first))
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for (auto bit : (*sigmap)(conn.second))
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sigbit_users_count[bit]++;
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}
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}
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void FfMergeHelper::clear() {
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dff_driver.clear();
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dff_sink.clear();
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sigbit_users_count.clear();
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}
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