mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-05 17:14:08 +00:00
12 lines
258 B
Verilog
12 lines
258 B
Verilog
module \$_DLATCH_N_ (E, D, Q);
|
|
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
|
|
input E, D;
|
|
output Q = !E ? D : Q;
|
|
endmodule
|
|
|
|
module \$_DLATCH_P_ (E, D, Q);
|
|
wire [1023:0] _TECHMAP_DO_ = "simplemap; opt";
|
|
input E, D;
|
|
output Q = E ? D : Q;
|
|
endmodule
|