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14 lines
579 B
Verilog
14 lines
579 B
Verilog
`default_nettype none
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// D flip-flop with async reset and enable
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module \$_DFFE_PN0P_ (input D, C, R, E, output Q);
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(C), .ACLR(R), .ENA(E), .SCLR(1'b0), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));
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endmodule
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// D flip-flop with sync reset and enable (enable has priority)
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module \$_SDFFCE_PP0P_ (input D, C, R, E, output Q);
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wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
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MISTRAL_FF _TECHMAP_REPLACE_(.DATAIN(D), .CLK(C), .ACLR(1'b1), .ENA(E), .SCLR(R), .SLOAD(1'b0), .SDATA(1'b0), .Q(Q));
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endmodule
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