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9018d06a33
The default mapping rules for division-like operations (div/divfloor/ mod/modfloor) invoke subtractions which can get mapped to carry chains in FPGA flows. Optimizations across carry chains are weak, so in practice this ends up too costly compared to implementing the division purely in soft logic. For this reason arrange for `techmap.v` ignoring division operations under `-D NODIV`, and use this mode in `synth_quicklogic` to avoid carry chains for divisions.
650 lines
17 KiB
Verilog
650 lines
17 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* The internal logic cell technology mapper.
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*
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* This Verilog library contains the mapping of internal cells (e.g. $not with
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* variable bit width) to the internal logic cells (such as the single bit $_NOT_
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* gate). Usually this logic network is then mapped to the actual technology
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* using e.g. the "abc" pass.
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*
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* Note that this library does not map $mem cells. They must be mapped to logic
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* and $dff cells using the "memory_map" pass first. (Or map it to custom cells,
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* which is of course highly recommended for larger memories.)
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*
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*/
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`define MIN(_a, _b) ((_a) < (_b) ? (_a) : (_b))
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`define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
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// --------------------------------------------------------
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// Use simplemap for trivial cell types
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// --------------------------------------------------------
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(* techmap_simplemap *)
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(* techmap_celltype = "$not $and $or $xor $xnor" *)
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module _90_simplemap_bool_ops;
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endmodule
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(* techmap_simplemap *)
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(* techmap_celltype = "$reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool" *)
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module _90_simplemap_reduce_ops;
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endmodule
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(* techmap_simplemap *)
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(* techmap_celltype = "$logic_not $logic_and $logic_or" *)
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module _90_simplemap_logic_ops;
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endmodule
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(* techmap_simplemap *)
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(* techmap_celltype = "$eq $eqx $ne $nex" *)
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module _90_simplemap_compare_ops;
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endmodule
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(* techmap_simplemap *)
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(* techmap_celltype = "$pos $slice $concat $mux $tribuf $bmux $bwmux $bweqx" *)
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module _90_simplemap_various;
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endmodule
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(* techmap_simplemap *)
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(* techmap_celltype = "$sr $ff $dff $dffe $adff $adffe $aldff $aldffe $sdff $sdffe $sdffce $dffsr $dffsre $dlatch $adlatch $dlatchsr" *)
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module _90_simplemap_registers;
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endmodule
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// --------------------------------------------------------
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// Shift operators
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// --------------------------------------------------------
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(* techmap_celltype = "$shr $shl $sshl $sshr" *)
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module _90_shift_ops_shr_shl_sshl_sshr (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter _TECHMAP_CELLTYPE_ = "";
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localparam shift_left = _TECHMAP_CELLTYPE_ == "$shl" || _TECHMAP_CELLTYPE_ == "$sshl";
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localparam sign_extend = A_SIGNED && _TECHMAP_CELLTYPE_ == "$sshr";
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] Y;
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localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH);
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localparam BB_WIDTH = `MIN($clog2(shift_left ? Y_WIDTH : A_SIGNED ? WIDTH : A_WIDTH) + 1, B_WIDTH);
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wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
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wire [1023:0] _TECHMAP_DO_01_ = "RECURSION; CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
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integer i;
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(* force_downto *)
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reg [WIDTH-1:0] buffer;
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reg overflow;
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always @* begin
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overflow = B_WIDTH > BB_WIDTH ? |B[B_WIDTH-1:BB_WIDTH] : 1'b0;
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buffer = overflow ? {WIDTH{sign_extend ? A[A_WIDTH-1] : 1'b0}} : {{WIDTH-A_WIDTH{A_SIGNED ? A[A_WIDTH-1] : 1'b0}}, A};
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for (i = 0; i < BB_WIDTH; i = i+1)
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if (B[i]) begin
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if (shift_left)
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buffer = {buffer, (2**i)'b0};
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else if (2**i < WIDTH)
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buffer = {{2**i{sign_extend ? buffer[WIDTH-1] : 1'b0}}, buffer[WIDTH-1 : 2**i]};
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else
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buffer = {WIDTH{sign_extend ? buffer[WIDTH-1] : 1'b0}};
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end
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end
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assign Y = buffer;
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endmodule
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(* techmap_celltype = "$shift $shiftx" *)
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module _90_shift_shiftx (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] Y;
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parameter _TECHMAP_CELLTYPE_ = "";
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
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localparam extbit = _TECHMAP_CELLTYPE_ == "$shift" ? 1'b0 : 1'bx;
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wire a_padding = _TECHMAP_CELLTYPE_ == "$shiftx" ? extbit : (A_SIGNED ? A[A_WIDTH-1] : 1'b0);
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localparam BB_WIDTH = `MIN($clog2(`MAX(A_WIDTH, Y_WIDTH)) + (B_SIGNED ? 2 : 1), B_WIDTH);
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localparam WIDTH = `MAX(A_WIDTH, Y_WIDTH) + (B_SIGNED ? 2**(BB_WIDTH-1) : 0);
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wire [1023:0] _TECHMAP_DO_00_ = "proc;;";
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wire [1023:0] _TECHMAP_DO_01_ = "CONSTMAP; opt_muxtree; opt_expr -mux_undef -mux_bool -fine;;;";
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integer i;
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(* force_downto *)
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reg [WIDTH-1:0] buffer;
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reg overflow;
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always @* begin
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overflow = 0;
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buffer = {WIDTH{extbit}};
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buffer[Y_WIDTH-1:0] = {Y_WIDTH{a_padding}};
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buffer[A_WIDTH-1:0] = A;
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if (B_WIDTH > BB_WIDTH) begin
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if (B_SIGNED) begin
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for (i = BB_WIDTH; i < B_WIDTH; i = i+1)
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if (B[i] != B[BB_WIDTH-1])
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overflow = 1;
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end else
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overflow = |B[B_WIDTH-1:BB_WIDTH];
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if (overflow)
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buffer = {WIDTH{extbit}};
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end
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if (B_SIGNED && B[BB_WIDTH-1])
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buffer = {buffer, {2**(BB_WIDTH-1){extbit}}};
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for (i = 0; i < (B_SIGNED ? BB_WIDTH-1 : BB_WIDTH); i = i+1)
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if (B[i]) begin
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if (2**i < WIDTH)
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buffer = {{2**i{extbit}}, buffer[WIDTH-1 : 2**i]};
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else
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buffer = {WIDTH{extbit}};
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end
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end
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assign Y = buffer;
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endmodule
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// --------------------------------------------------------
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// Arithmetic operators
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// --------------------------------------------------------
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(* techmap_celltype = "$fa" *)
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module _90_fa (A, B, C, X, Y);
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parameter WIDTH = 1;
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(* force_downto *)
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input [WIDTH-1:0] A, B, C;
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(* force_downto *)
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output [WIDTH-1:0] X, Y;
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(* force_downto *)
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wire [WIDTH-1:0] t1, t2, t3;
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assign t1 = A ^ B, t2 = A & B, t3 = C & t1;
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assign Y = t1 ^ C, X = t2 | t3;
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endmodule
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(* techmap_celltype = "$lcu" *)
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module _90_lcu_brent_kung (P, G, CI, CO);
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parameter WIDTH = 2;
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(* force_downto *)
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input [WIDTH-1:0] P, G;
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input CI;
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(* force_downto *)
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output [WIDTH-1:0] CO;
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integer i, j;
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(* force_downto *)
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reg [WIDTH-1:0] p, g;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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always @* begin
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p = P;
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g = G;
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// in almost all cases CI will be constant zero
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g[0] = g[0] | (p[0] & CI);
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// [[CITE]] Brent Kung Adder
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// R. P. Brent and H. T. Kung, "A Regular Layout for Parallel Adders",
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// IEEE Transaction on Computers, Vol. C-31, No. 3, p. 260-264, March, 1982
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// Main tree
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for (i = 1; i <= $clog2(WIDTH); i = i+1) begin
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for (j = 2**i - 1; j < WIDTH; j = j + 2**i) begin
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g[j] = g[j] | p[j] & g[j - 2**(i-1)];
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p[j] = p[j] & p[j - 2**(i-1)];
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end
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end
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// Inverse tree
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for (i = $clog2(WIDTH); i > 0; i = i-1) begin
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for (j = 2**i + 2**(i-1) - 1; j < WIDTH; j = j + 2**i) begin
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g[j] = g[j] | p[j] & g[j - 2**(i-1)];
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p[j] = p[j] & p[j - 2**(i-1)];
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end
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end
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end
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assign CO = g;
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endmodule
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(* techmap_celltype = "$alu" *)
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module _90_alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] CO;
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(* force_downto *)
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wire [Y_WIDTH-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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\$lcu #(.WIDTH(Y_WIDTH)) lcu (.P(X), .G(AA & BB), .CI(CI), .CO(CO));
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assign X = AA ^ BB;
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assign Y = X ^ {CO, CI};
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endmodule
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(* techmap_maccmap *)
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(* techmap_celltype = "$macc" *)
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module _90_macc;
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endmodule
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(* techmap_wrap = "alumacc" *)
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(* techmap_celltype = "$lt $le $ge $gt $add $sub $neg $mul" *)
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module _90_alumacc;
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endmodule
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// --------------------------------------------------------
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// Divide and Modulo
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// --------------------------------------------------------
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`ifndef NODIV
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module \$__div_mod_u (A, B, Y, R);
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parameter WIDTH = 1;
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(* force_downto *)
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input [WIDTH-1:0] A, B;
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(* force_downto *)
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output [WIDTH-1:0] Y, R;
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(* force_downto *)
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wire [WIDTH*WIDTH-1:0] chaindata;
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assign R = chaindata[WIDTH*WIDTH-1:WIDTH*(WIDTH-1)];
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genvar i;
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generate begin
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for (i = 0; i < WIDTH; i=i+1) begin:stage
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(* force_downto *)
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wire [WIDTH-1:0] stage_in;
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if (i == 0) begin:cp
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assign stage_in = A;
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end else begin:cp
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assign stage_in = chaindata[i*WIDTH-1:(i-1)*WIDTH];
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end
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assign Y[WIDTH-(i+1)] = stage_in >= {B, {WIDTH-(i+1){1'b0}}};
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assign chaindata[(i+1)*WIDTH-1:i*WIDTH] = Y[WIDTH-(i+1)] ? stage_in - {B, {WIDTH-(i+1){1'b0}}} : stage_in;
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end
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end endgenerate
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endmodule
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// truncating signed division/modulo
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module \$__div_mod_trunc (A, B, Y, R);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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localparam WIDTH =
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A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
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B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] Y, R;
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(* force_downto *)
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wire [WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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(* force_downto *)
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wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u;
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assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
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assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
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\$__div_mod_u #(
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.WIDTH(WIDTH)
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) div_mod_u (
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.A(A_buf_u),
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.B(B_buf_u),
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.Y(Y_u),
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.R(R_u)
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);
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assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? -Y_u : Y_u;
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assign R = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
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endmodule
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(* techmap_celltype = "$div" *)
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module _90_div (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] Y;
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\$__div_mod_trunc #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) div_mod (
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.A(A),
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.B(B),
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.Y(Y)
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);
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endmodule
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(* techmap_celltype = "$mod" *)
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module _90_mod (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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(* force_downto *)
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output [Y_WIDTH-1:0] Y;
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\$__div_mod_trunc #(
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.A_SIGNED(A_SIGNED),
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.B_SIGNED(B_SIGNED),
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.A_WIDTH(A_WIDTH),
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.B_WIDTH(B_WIDTH),
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.Y_WIDTH(Y_WIDTH)
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) div_mod (
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.A(A),
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.B(B),
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.R(Y)
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);
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endmodule
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// flooring signed division/modulo
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module \$__div_mod_floor (A, B, Y, R);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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localparam WIDTH =
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A_WIDTH >= B_WIDTH && A_WIDTH >= Y_WIDTH ? A_WIDTH :
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B_WIDTH >= A_WIDTH && B_WIDTH >= Y_WIDTH ? B_WIDTH : Y_WIDTH;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y, R;
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wire [WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
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wire [WIDTH-1:0] A_buf_u, B_buf_u, Y_u, R_u, R_s;
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assign A_buf_u = A_SIGNED && A_buf[WIDTH-1] ? -A_buf : A_buf;
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assign B_buf_u = B_SIGNED && B_buf[WIDTH-1] ? -B_buf : B_buf;
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\$__div_mod_u #(
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.WIDTH(WIDTH)
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) div_mod_u (
|
|
.A(A_buf_u),
|
|
.B(B_buf_u),
|
|
.Y(Y_u),
|
|
.R(R_u)
|
|
);
|
|
|
|
// For negative results, if there was a remainder, subtract one to turn
|
|
// the round towards 0 into a round towards -inf
|
|
assign Y = A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? (R_u == 0 ? -Y_u : -Y_u-1) : Y_u;
|
|
|
|
// truncating modulo
|
|
assign R_s = A_SIGNED && B_SIGNED && A_buf[WIDTH-1] ? -R_u : R_u;
|
|
// Flooring modulo differs from truncating modulo only if it is nonzero and
|
|
// A and B have different signs - then `floor - trunc = B`
|
|
assign R = (R_s != 0) && A_SIGNED && B_SIGNED && (A_buf[WIDTH-1] != B_buf[WIDTH-1]) ? $signed(B_buf) + $signed(R_s) : R_s;
|
|
endmodule
|
|
|
|
(* techmap_celltype = "$divfloor" *)
|
|
module _90_divfloor (A, B, Y);
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
(* force_downto *)
|
|
input [A_WIDTH-1:0] A;
|
|
(* force_downto *)
|
|
input [B_WIDTH-1:0] B;
|
|
(* force_downto *)
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
\$__div_mod_floor #(
|
|
.A_SIGNED(A_SIGNED),
|
|
.B_SIGNED(B_SIGNED),
|
|
.A_WIDTH(A_WIDTH),
|
|
.B_WIDTH(B_WIDTH),
|
|
.Y_WIDTH(Y_WIDTH)
|
|
) div_mod (
|
|
.A(A),
|
|
.B(B),
|
|
.Y(Y)
|
|
);
|
|
endmodule
|
|
|
|
(* techmap_celltype = "$modfloor" *)
|
|
module _90_modfloor (A, B, Y);
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
(* force_downto *)
|
|
input [A_WIDTH-1:0] A;
|
|
(* force_downto *)
|
|
input [B_WIDTH-1:0] B;
|
|
(* force_downto *)
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
\$__div_mod_floor #(
|
|
.A_SIGNED(A_SIGNED),
|
|
.B_SIGNED(B_SIGNED),
|
|
.A_WIDTH(A_WIDTH),
|
|
.B_WIDTH(B_WIDTH),
|
|
.Y_WIDTH(Y_WIDTH)
|
|
) div_mod (
|
|
.A(A),
|
|
.B(B),
|
|
.R(Y)
|
|
);
|
|
endmodule
|
|
`endif
|
|
|
|
// --------------------------------------------------------
|
|
// Power
|
|
// --------------------------------------------------------
|
|
|
|
(* techmap_celltype = "$pow" *)
|
|
module _90_pow (A, B, Y);
|
|
parameter A_SIGNED = 0;
|
|
parameter B_SIGNED = 0;
|
|
parameter A_WIDTH = 1;
|
|
parameter B_WIDTH = 1;
|
|
parameter Y_WIDTH = 1;
|
|
|
|
(* force_downto *)
|
|
input [A_WIDTH-1:0] A;
|
|
(* force_downto *)
|
|
input [B_WIDTH-1:0] B;
|
|
(* force_downto *)
|
|
output [Y_WIDTH-1:0] Y;
|
|
|
|
wire _TECHMAP_FAIL_ = 1;
|
|
endmodule
|
|
|
|
|
|
// --------------------------------------------------------
|
|
// Parallel Multiplexers
|
|
// --------------------------------------------------------
|
|
|
|
(* techmap_celltype = "$pmux" *)
|
|
module _90_pmux (A, B, S, Y);
|
|
parameter WIDTH = 1;
|
|
parameter S_WIDTH = 1;
|
|
|
|
(* force_downto *)
|
|
input [WIDTH-1:0] A;
|
|
(* force_downto *)
|
|
input [WIDTH*S_WIDTH-1:0] B;
|
|
(* force_downto *)
|
|
input [S_WIDTH-1:0] S;
|
|
(* force_downto *)
|
|
output [WIDTH-1:0] Y;
|
|
|
|
(* force_downto *)
|
|
wire [WIDTH-1:0] Y_B;
|
|
|
|
genvar i, j;
|
|
generate
|
|
(* force_downto *)
|
|
wire [WIDTH*S_WIDTH-1:0] B_AND_S;
|
|
for (i = 0; i < S_WIDTH; i = i + 1) begin:B_AND
|
|
assign B_AND_S[WIDTH*(i+1)-1:WIDTH*i] = B[WIDTH*(i+1)-1:WIDTH*i] & {WIDTH{S[i]}};
|
|
end:B_AND
|
|
for (i = 0; i < WIDTH; i = i + 1) begin:B_OR
|
|
(* force_downto *)
|
|
wire [S_WIDTH-1:0] B_AND_BITS;
|
|
for (j = 0; j < S_WIDTH; j = j + 1) begin:B_AND_BITS_COLLECT
|
|
assign B_AND_BITS[j] = B_AND_S[WIDTH*j+i];
|
|
end:B_AND_BITS_COLLECT
|
|
assign Y_B[i] = |B_AND_BITS;
|
|
end:B_OR
|
|
endgenerate
|
|
|
|
assign Y = |S ? Y_B : A;
|
|
endmodule
|
|
|
|
// --------------------------------------------------------
|
|
// Demultiplexers
|
|
// --------------------------------------------------------
|
|
|
|
(* techmap_celltype = "$demux" *)
|
|
module _90_demux (A, S, Y);
|
|
parameter WIDTH = 1;
|
|
parameter S_WIDTH = 1;
|
|
|
|
(* force_downto *)
|
|
input [WIDTH-1:0] A;
|
|
(* force_downto *)
|
|
input [S_WIDTH-1:0] S;
|
|
(* force_downto *)
|
|
output [(WIDTH << S_WIDTH)-1:0] Y;
|
|
|
|
generate
|
|
if (S_WIDTH == 0) begin
|
|
assign Y = A;
|
|
end else if (S_WIDTH == 1) begin
|
|
assign Y[0+:WIDTH] = S ? 0 : A;
|
|
assign Y[WIDTH+:WIDTH] = S ? A : 0;
|
|
end else begin
|
|
localparam SPLIT = S_WIDTH / 2;
|
|
wire [(1 << (S_WIDTH-SPLIT))-1:0] YH;
|
|
wire [(1 << SPLIT)-1:0] YL;
|
|
$demux #(.WIDTH(1), .S_WIDTH(SPLIT)) lo (.A(1'b1), .S(S[SPLIT-1:0]), .Y(YL));
|
|
$demux #(.WIDTH(1), .S_WIDTH(S_WIDTH-SPLIT)) hi (.A(1'b1), .S(S[S_WIDTH-1:SPLIT]), .Y(YH));
|
|
genvar i;
|
|
for (i = 0; i < (1 << S_WIDTH); i = i + 1) begin
|
|
localparam [S_WIDTH-1:0] IDX = i;
|
|
assign Y[i*WIDTH+:WIDTH] = (YL[IDX[SPLIT-1:0]] & YH[IDX[S_WIDTH-1:SPLIT]]) ? A : 0;
|
|
end
|
|
end
|
|
endgenerate
|
|
endmodule
|
|
|
|
|
|
// --------------------------------------------------------
|
|
// LUTs
|
|
// --------------------------------------------------------
|
|
|
|
`ifndef NOLUT
|
|
(* techmap_simplemap *)
|
|
(* techmap_celltype = "$lut $sop" *)
|
|
module _90_lut;
|
|
endmodule
|
|
`endif
|
|
|