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0f96ae5990
Some builtin cells have an undefined (x) output even when all inputs are defined. This is not natively supported by the formal backends which will produce a fully defined value instead. This can lead to issues when combining different backends in a formal flow. To work around these, this adds a file containing verilog implementation of cells matching the fully defined behavior implemented by the smt2 backend.
29 lines
654 B
Verilog
29 lines
654 B
Verilog
(* techmap_celltype = "$pmux" *)
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module smt_pmux (A, B, S, Y);
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parameter WIDTH = 1;
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parameter S_WIDTH = 1;
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(* force_downto *)
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input [WIDTH-1:0] A;
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(* force_downto *)
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input [WIDTH*S_WIDTH-1:0] B;
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(* force_downto *)
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input [S_WIDTH-1:0] S;
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(* force_downto *)
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output [WIDTH-1:0] Y;
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(* force_downto *)
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wire [WIDTH-1:0] Y_B;
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genvar i, j;
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generate
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(* force_downto *)
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wire [WIDTH*(S_WIDTH+1)-1:0] C;
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assign C[WIDTH-1:0] = A;
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for (i = 0; i < S_WIDTH; i = i + 1)
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assign C[WIDTH*(i+2)-1:WIDTH*(i+1)] = S[i] ? B[WIDTH*(i+1)-1:WIDTH*i] : C[WIDTH*(i+1)-1:WIDTH*i];
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assign Y = C[WIDTH*(S_WIDTH+1)-1:WIDTH*S_WIDTH];
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endgenerate
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endmodule
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